DCF77 Radio Clock Module with High-Sensitivity Antenna and MCU

SISINKAL

DCF77 Radio Clock Module with High-Sensitivity Antenna and MCU

£49.57 £82.62
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Description

  • DCF77 receiver module for 77.5 kHz time signals
  • Precise reception and synchronization of date and time signals
  • Supports DCF/77.5 kHz single-frequency and JJY/40 + 60 kHz dual-frequency specifications
  • Compact PCB: 25.0 11.5 1.0 mm for DCF; 22.0 13.5 1.0 mm for JJY
  • AR10 60 mm high-Q antenna
  • Operating voltage: 1.13.3 V
  • Maximum current consumption: 85 A
  • Includes 1 DCF receiver module with antenna


DCF receiver module with an antenna tuned to the DCF77 time-signal transmitter at 77.5 kHz near Frankfurt. The antenna induction signal is sent to the IC for amplification and demodulation, then identified by the MCU to enable accurate synchronization with the date and time from the timing center. Setup and wiring diagrams are provided below. Technical specifications: DCF 77.5 kHz single-frequency specification: - Part number: DCF-1060N-03A - RCCM category: DCF/77.5 kHz single-frequency module - PCB size: 25.0 11.5 1.0 mm, FR4 - Antenna size: AR10 60 mm, high Q - Nominal frequency: 77.5 kHz 300 Hz - Sensitivity: 27 2 dB - Receiver IC: CME6005 JJY 40/60 kHz dual-frequency specification: - Product number: JJY-1060N-MAS - RCCM category: JJY/40 + 60 kHz dual-frequency module - PCB size: 22.0 13.5 1.0 mm, FR4 - Antenna size: AR10 60 mm, high Q - Nominal frequency: 40/60 kHz 300 Hz - Sensitivity: 40/60 kHz: 30/28 2 dB - Receiver IC: MAS6181B Operating voltage: 1.13.3 V. Maximum current consumption: 85 A. Reception frequency: 77.5 kHz. PCB size without antenna (L W H): 22 13.5 1 mm. Antenna size (L W): 60 10 mm. Connections: - Ground = pin - Supply voltage = pin - Data = pin T - On/off control = pin P1 - 40/60 kHz frequency selection = SEL pin AGC note 4 optional AGC on/hold control: The AON control pin has an internal pull-up. When the AON pin is not connected, the AGC circuit remains on. The AON control can optionally be used to hold and release the AGC circuit. A stepper motor driving an analog clock may generate interference that shifts the input gain away from its optimal level. This can be avoided by controlling AGC hold (AON = VSS) during stepper motor operation and releasing the AGC (AON = VDD) when no motors are operating. AGC should only be held during interference and released at other times, because leakage can still cause the AGC level to change slowly while it is held.

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DCF77 Radio Clock Module with High-Sensitivity Antenna and MCU

SiSinkal.

DCF77 Radio Clock Module with High-Sensitivity Antenna an...

£49.57 £82.62